There are known methods for proving the design worthiness of an electronic circuit prior to committing extensive resources to making it in production quantities. Traditional methods include making a number of prototypes of the circuit and subjecting them to laboratory testing. This method is time consuming and expensive, and often requires the use of not readily available, state-of-the-art electronic components. When circuit faults are found, corrections to the prototypes take time and are prone to error. The fast-moving pace of the electronics marketplace demands a more rapid way of developing products using such circuits.
Electronic circuit designers have long appreciated the value of using computers to simulate circuit designs. Simulation promises a faster and less expensive circuit design process alternative because design faults can be found and eliminated before an actual circuit is produced. In practice, simulation often eliminates the circuit prototyping step and is virtually essential to integrated circuit development.
However, simulation has not always been successful for proving the design worthiness of boardlevel circuits and complex integrated circuits. Such designs are characterized by a mix of synchronous and asynchronous logic functions and typically include multiple complex circuits, some of which are still in development during simulation. The simulation of such designs requires extensive computer time, and the accuracy of the simulation results is often questionable. The expense of computer time and the engineering time required to program the simulation, together with the risk of questionable results, has led many circuit designers to simply "give up" on simulation as a practical alternative to prototyping.
The above realization has created a market for faster and more easily usable simulators that are capable of accurately simulating highly complex logic circuits. Representative simulators include Verilog-XL.TM. available from Cadence Design Systems, San Jose, Calif.; QuickSim.TM. and QuickSim II.TM. available from Mentor Graphics Corporation, Wilsonville, Oreg.; and ViewSim.TM. available from Viewlogic Systems, Inc., Marlboro, Mass.
FIG. 1 shows the relationship between a typical prior art circuit development process 10 and the accuracy or specificity of the circuit design corresponding to each step of the process.
At the highest, least accurate level, the circuit is described only in terms of a design specification or architectural description 12 of a product in which the circuit will be used.
A behavior level 14 description is more design specific and describes the circuit in functional block diagram terms such as, for example, counters, processors, or registers.
A register transfer logic level 16 describes the circuit design by the interconnection of functional blocks in terms such as processor instructions, counter values, bus bit-widths, and Boolean logic expressions.
A gate level 18 describes each functional block as detailed interconnections of logic function symbols.
A switch level 20 describes the logic symbols of the gate level in terms of transistor level circuit designs.
A layout level 22 describes the topological or physical positioning and electrical interconnections of the above-described circuit design elements. If the circuit design is implemented on an etched circuit board, the layout level is the lowest required design level.
If the circuit design is implemented on an integrated circuit, the layout level is further sub-divided into a silicon design level 24 comprising multiple mask layers delineating the fabrication steps of the integrated circuit.
Design accuracy generally increases toward the lower levels of the circuit development process. However, for a given design, simulation at lower levels requires additional computer time to analyze the added complexity inherent at lower levels. There is, therefore, a tradeoff between design accuracy and simulation performance.
Because typical circuit designs include a mix of subcircuits, some well understood and others untested, a technique known as "mixed-mode" simulation has evolved. Mixed-mode simulation typically employs behavior level models of well-understood subcircuits, such as purchased components, and gate level models of untested sub-circuits as a trade-off between design accuracy and simulation performance.
Behavior level 14 simulation models of commercially available logic components are typically manually programmed by the designers of the larger circuit being simulated. Manual programming is a time-consuming, error prone task.
Recently, behavioral level 14 models of commercially available logic components have become available. For example, the Logic Automation Description Language ("LADL"), available from Logic Modeling Corporation, the assignee of the present application, provides a library of accurate simulation models for a wide variety of commercially available components. Circuit designers using LADL models are relieved from manually programming conventional logic components to concentrate on developing their proprietary circuit design and associated simulation model programs. The resulting simulation requires reduced model programming time and produces reasonably accurate results.
Market acceptance of commercially available simulation models has created a demand for simulation models of more complex components such as peripheral controllers, microprocessors, and memories. Moreover, circuit designers demand gate level 18 models in addition to behavior level 14 models to support the accuracy required by complex circuit simulations. Indeed, some simulators will not operate in mixed-mode. Developing accurate gate level 18 simulation models of complex components requires automated model development tools.
FIG. 2 shows an exemplary prior art automated simulation model generation process. A circuit design is stored in a structural data file 30 such as the standard Electronic Design Interchange Format ("EDIF"). Structural data file 30 typically includes data not required for a simulation model, so structural data file 30 is translated by a data translator 32 into a net-list 34 readable by a simulation model compiler 36. Simulation model compiler 36 performs various steps on net-list 34 including structural partitioning and assignment of execution time levels, referred to as "levelization." When model compiler 36 is finished, an output translator 38 translates the compiled model into a model file 40 compatible with the requirements of a particular simulator 42.
Development of such simulation automation tools is a major focus of development efforts in the electronic design automation field. For instance, Wang, Hoover, Porter, et al, in "SSIM: A Software Levelized Compiled-Code Simulator", Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, describe levelization and simulation techniques that increase the performance of simulating synchronous logic circuits. They also state that circuits having feedback loops cannot be levelized.
Maurer and Wang in "Techniques for Unit-Delay Compiled Simulation", Proceedings of the 27th ACM/IEEE Design Automation Conference, 1990, describe performance and accuracy improvements in simulating logic circuit time delays. Again, the results do not apply to asynchronous logic circuits.
Wang and Maurer in "LECSIM: A Levelized Event Driven Compiled Logic Simulator" Proceedings of the 27th ACM/IEEE Design Automation Conference, 1990, describe techniques for levelizing circuit models containing feedback loops. However, functional evaluation problems associated with feedback loops are not addressed.
The above-described work has been successful whenever the modeled circuit is entirely synchronous. However, net-lists for highly complex circuits, such as integrated circuits, when translated into simulation models by conventional techniques, exhibit timing and functional evaluation errors. Such errors are not surprising because integrated circuits often have system bus control and distributed clocking subcircuits that exhibit asynchronous behavior. Technology trends suggest that integrated circuits are becoming more like "systems on chips" that actually require the extensive use of asynchronous, "self-timed" subcircuits.
U.S. Pat. No. 4,342,093 of Miyoshi for METHOD OF DIGITAL LOGIC SIMULATION describes an alternative automated simulation model generating approach. A simulation system substitutes the functionality of an actual component into the simulation model of a larger circuit whenever the simulator requires a functional evaluation of the component. This technique works well where software models of complex integrated circuits are unavailable. However, the hardware needed to support such simulation modeling is expensive and is useless if the component being modeled is unavailable or is still under development and not functioning properly.
What is needed, therefore, is a system and an automated method for generating an accurate simulation model of a complex synchronous/asynchronous logic circuit from a structural data description of the circuit.